1. Field of the Invention
The present invention relates to crystal oscillator circuits and, more particularly, to a crystal oscillator circuit that has a start-up time reduction circuit.
2. Description of the Related Art
An oscillator is a circuit that outputs a periodic signal. FIG. 1 shows a schematic diagram that illustrates a prior-art, quartz-crystal oscillator circuit 100. As shown in FIG. 1, crystal oscillator circuit 100, which is also known as a Pierce oscillator, includes a crystal circuit 110 that has a quartz crystal 112 and a bias resistor R.
Quartz crystal 112, in turn, has a first terminal that is connected to a first node N1, and a second terminal that is connected to a second node N2. Further, bias resistor R also has a first terminal that is connected to the first node N1, and a second terminal that is connected to the second node N2.
In addition, crystal oscillator circuit 100 includes a first capacitor 114 that has a first plate connected to the first node N1 and a second plate connected to ground, and a second capacitor 116 that has a first plate connected to the second node N2 and a second plate connected to ground.
Crystal oscillator circuit 100 further includes a logic device 120 that has an odd number of serially-connected inverters, including a first inverter 120A that is connected to the first node N1, a last inverter 120B that is connected to the second node N2, and a next-to-last inverter 120C that is connected to last inverter 120B. Logic device 120 also has an output inverter 120D that is connected to the input of last inverter 120B to output a clock signal CLK.
In operation, when power is first applied, crystal oscillator circuit 100 produces an oscillating signal OS on the first node N1 that builds in magnitude over a period of time until the magnitude of the oscillating signal OS reaches a final steady state level. A start-up period, in turn, is typically defined as the time from when power is first applied to when the magnitude of the oscillating signal reaches approximately 85%–90% of the final steady state level.
FIG. 2 shows a timing diagram that illustrates the start-up period of crystal oscillator circuit 100. During power up, noise is amplified by oscillator circuit 100. As shown in FIG. 2, through the filtering property of the quartz crystal, only the natural frequency of the crystal is amplified to produce an oscillating signal OS, while the other frequencies are attenuated. As further shown in FIG. 2, oscillating signal OS has an envelope 210 that builds in magnitude over the start-up period, which extends from time t0 to time t1.
In many applications, a shorter start-up time is desirable. One approach to reducing the start-up time of a crystal oscillator circuit is to increase the gain in the crystal oscillator circuit. Increasing the gain to reduce the start-up time, however, can hasten the aging of the crystal, and hence prematurely degrade the accuracy and reliability of the crystal.
Another approach to reducing the start-up time of a crystal oscillator circuit is to provide additional gain during the start-up period, and then shut off the additional gain after the oscillation has been deemed to be “stable” (e.g., reached approximately 85%–90% of the final steady state level). Since the extra gain is provided only during the start-up period, the negative effect on the crystal is relatively minor.
However, one problem with the prior approaches to providing additional gain only during the start-up period is that these prior approaches lack any mechanism to re-apply the extra gain to aid the build up of oscillation if the determination of a “stable” oscillation is incorrect, or for any reason the oscillation is interrupted. Thus, there is a need for an approach to reducing the start-up time of a quartz-crystal oscillator circuit that eliminates the above limitations.